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1

Lenguaje de Descripción de Hardware VHDL / codigo en vhdl pwm basys2

« en: Viernes 18 de Mayo de 2012, 06:46 »

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY pwmokk is
generic( Max: natural := 1000000);
Port ( clk : in STD_LOGIC;--reloj de 50MHz
selector : in STD_LOGIC_VECTOR (1 downto 0);--selecciona las 4 posiciones
PWM : out STD_LOGIC);--terminal donde sale la señal de PWM
end pwmokk;

ARCHITECTURE behavioral of pwmokk is
signal PWM_Count: integer range 1 to max;--1000000;
constant pos1: integer := 15000;
constant pos2: integer := 125000;
constant pos3: integer := 150000;
constant pos4: integer := 230000;

begin
process( clk,PWM_Count,selector)
begin
if rising_edge(clk)then
PWM_Count <= PWM_Count + 1;
end if;

case (selector) is
when "00" =>
if PWM_Count <= pos1 then
PWM <= '1';
else PWM <= '0';
end if;
when "01" =>
if PWM_Count <= pos2 then
PWM <= '1';
else PWM <= '0';
end if;
when "10" =>
if PWM_Count <= pos3
then PWM <= '1';
else PWM <= '0';
end if;
when others =>
if PWM_Count <= pos4 then
PWM <= '1';
else PWM <= '0';
end if;
end case;
end process;
end behavioral;

2

Lenguaje de Descripción de Hardware VHDL / memoria rom en vhdl

« en: Viernes 18 de Mayo de 2012, 06:32 »

Programa que muestra por 4 leds, el valor almacenado en cada una de las direcciones de memoria
para acceder alas direcciones se pulsa un push buton el cual incrementa un contador el cual ira leyendo los diferentes valores guardados
tarjeta utilizada basys 2
si desean el archivo ucf o cualquier aclaracion enviar un correo a tico_x@live.com.mx

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.Std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;

entity rams_21b is
Port ( clk : in STD_LOGIC;
en : in STD_LOGIC;
data : out STD_LOGIC_VECTOR (3 downto 0));
end rams_21b;

architecture Behavioral of rams_21b is
type rom_type is array (0 to 15) of std_logic_vector (3 downto 0);
constant ROM : rom_type :=(x"0",x"1",x"2",x"3",x"4",x"5",
"0110","0111","1000","1001","1010",
"1011","1100","1101","1110","1111");

signal addr : std_logic_vector(3 downto 0);
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (en = '1') then
addr <= addr +1;
else
addr <= addr -1;
end if;
end if;
end process;
data <= ROM(conv_integer(addr));
end Behavioral;

3

Lenguaje de Descripción de Hardware VHDL / multiplicador de 4 bits vhdl

« en: Viernes 18 de Mayo de 2012, 06:26 »

programa que multiplica 2 numeros de 4 bits el resultado es mostrado por los display de 7 segmentos tarjeta utilizada basys 2
El codigo en vhdl es el siguiente

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.Std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;

entity bcd is
Port ( clr,mclk : in STD_LOGIC;
     punto : out std_logic;
           a,x : in std_logic_vector (3 downto 0);
     y : out std_logic_vector (3 downto 0);
           c : out STD_LOGIC_VECTOR (7 downto 0);
d : out STD_LOGIC_VECTOR (6 downto 0));
end bcd;

architecture Behavioral of bcd is
signal b : STD_LOGIC_VECTOR (7 downto 0);
signal unidades,decenas,centenas,sal : STD_LOGIC_VECTOR (3 downto 0);
signal clk2 : std_logic;
signal qq : STD_LOGIC_VECTOR (10 downto 0);
signal count : STD_LOGIC_VECTOR (1 downto 0);

begin
process(a,x,clr)
begin
if clr = '1' then
b <= x"00";
else
b <= (a*x);
end if;
end process;

--**********convertidor binario a bcd para vizualizar en 3 display unidades decenas centanas**********
process(

variable z: STD_LOGIC_VECTOR (19 downto 0);
begin
for i in 0 to 19 loop
z(i) := '0';
end loop;
z(10 downto 3) := B;
for i in 0 to 4 loop
if z(11 downto 8) > 4 then
z(11 downto 8) := z(11 downto 8) + 3;
end if;
if z(15 downto 12) > 4 then
z(15 downto 12) := z(15 downto 12) + 3;
end if;
z(19 downto 1) := z(18 downto 0);
end loop;
unidades <= z(19 downto 16);
decenas <= z(15 downto 12);
centenas <= z(11 downto 8);
end process ;

process(mclk) begin
if rising_edge(mclk) then
qq <= qq + 1;
end if;
end process;

clk2 <= qq(10);

--***********bcd a 7 segmentos**********
process(sal) begin
case sal is
when X"0" => d <= "0000001"; --0
when X"1" => d <= "1001111"; --1
when X"2" => d <= "0010010"; --2
when X"3" => d <= "0000110"; --3
when X"4" => d <= "1001100"; --4
when X"5" => d <= "0100100"; --5
when X"6" => d <= "0100000"; --6
when X"7" => d <= "0001101"; --7
when X"8" => d <= "0000000"; --8
when others => d <= "0000100"; --9
end case;
end process;

--***************multiplexion del display***********
process(count,unidades,decenas,centenas,clk2)
begin
if rising_edge(clk2) then
count <= count + 1;
if count = "11" then
count <= "00";
end if;
end if;
case count is
when "00" => sal <= unidades;
y <= x"b";
when "01" => sal <= decenas;
y <= x"d";
when others => sal <= centenas;
y <= x"e";
end case;
end process;
punto <= '1';
c <=b;
end Behavioral;

4

Lenguaje de Descripción de Hardware VHDL / Re:Conversor Binario A Bcd De 11 Bits

« en: Viernes 18 de Mayo de 2012, 06:16 »

Adjunto el codigo de un convertidor binario a bcd de 12 bits,
el programa es un contador de 12 bits cada que se pulsa un push botton aumenta su valor en uno
la valor de la cuenta es mostrada en 4 display, el programa esta en vhdl
se utiliza la tarjeta basys 2 , para cualquier duda envienme un correo a tico_x@live.com.mx

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.Std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;

entity bcd is
Port ( mclk,kl,up,clr : in STD_LOGIC;
punto : out std_logic;
y : out std_logic_vector (3 downto 0);
d : out STD_LOGIC_VECTOR (6 downto 0));
end bcd;

architecture Behavioral of bcd is
signal b : STD_LOGIC_VECTOR (11 downto 0);
signal unidades,decenas,centenas,millares,sal : STD_LOGIC_VECTOR (3 downto 0);
signal clk2 : std_logic;
signal qq : STD_LOGIC_VECTOR (10 downto 0);
signal count : STD_LOGIC_VECTOR (1 downto 0);
signal dd : STD_LOGIC_VECTOR (7 downto 0);
--********contador de 12 bits rango 0-40955**********
begin
process(kl, clr)
begin
if clr = '1' then
b <= (others => '0');
elsif rising_edge(kl) then
if (up='0')then
b <= b + 1;
else
b <= b - 1;
end if;
end if;
end process;

--**********convertidor binario a bcd para vizualizar en 4 display unidades decenas centenas millares**********
process(

variable z: STD_LOGIC_VECTOR (27 downto 0);
begin
for i in 0 to 27 loop
z(i) := '0';
end loop;
z(14 downto 3) := B;

for i in 0 to 8 loop
if z(15 downto 12) > 4 then
z(15 downto 12) := z(15 downto 12) + 3;
end if;
if z(19 downto 16) > 4 then
z(19 downto 16) := z(19 downto 16) + 3;
end if;

if z(23 downto 20) > 4 then
z(23 downto 20) := z(23 downto 20) + 3;
end if;

if z(27 downto 24) > 4 then
z(27 downto 24) := z(27 downto 24) + 3;
end if;
z(27 downto 1) := z(26 downto 0);
end loop;
unidades <= z(27 downto 24);
decenas <= z(23 downto 20);
centenas <= z(19 downto 16);
millares <= z(15 downto 12);
end process ;

process(mclk) begin
if rising_edge(mclk) then
qq <= qq + 1;
end if;
end process;

--***********bcd a 7 segmentos**********
process(sal) begin
case sal is
when X"0" => dd <= x"01"; --0
when X"1" => dd <= x"4f"; --1
when X"2" => dd <= x"12"; --2
when X"3" => dd <= x"06"; --3
when X"4" => dd <= x"4c"; --4
when X"5" => dd <= x"24"; --5
when X"6" => dd <= x"20"; --6
when X"7" => dd <= x"0d"; --7
when X"8" => dd <= x"00"; --8
when others => dd <= x"04"; --9
end case;
end process;

--***************multiplexion del display***********
process(count,unidades,decenas,centenas,millares,clk2)
begin
if rising_edge(clk2) then
count <= count + 1;
end if;
case count is
when "00" => sal <= unidades;
y <= x"7";
when "01" => sal <= decenas;
y <= x"b";
when "10" => sal <= centenas;
y <= x"d";
when others => sal <= millares;
y <= x"e";
end case;
end process;
clk2 <= qq(10);
punto <= '1';
d <=dd(6 downto 0 );
end Behavioral;

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