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Programación Específica => Otros temas específicos => Lenguaje de Descripción de Hardware VHDL => Mensaje iniciado por: acorona en Viernes 18 de Mayo de 2012, 06:46
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY pwmokk is
generic( Max: natural := 1000000);
Port ( clk : in STD_LOGIC;--reloj de 50MHz
selector : in STD_LOGIC_VECTOR (1 downto 0);--selecciona las 4 posiciones
PWM : out STD_LOGIC);--terminal donde sale la señal de PWM
end pwmokk;
ARCHITECTURE behavioral of pwmokk is
signal PWM_Count: integer range 1 to max;--1000000;
constant pos1: integer := 15000;
constant pos2: integer := 125000;
constant pos3: integer := 150000;
constant pos4: integer := 230000;
begin
process( clk,PWM_Count,selector)
begin
if rising_edge(clk)then
PWM_Count <= PWM_Count + 1;
end if;
case (selector) is
when "00" =>
if PWM_Count <= pos1 then
PWM <= '1';
else PWM <= '0';
end if;
when "01" =>
if PWM_Count <= pos2 then
PWM <= '1';
else PWM <= '0';
end if;
when "10" =>
if PWM_Count <= pos3
then PWM <= '1';
else PWM <= '0';
end if;
when others =>
if PWM_Count <= pos4 then
PWM <= '1';
else PWM <= '0';
end if;
end case;
end process;
end behavioral;